1. Field of the Invention
The present invention relates to static random access memory circuits, and more particularly to static random access memory circuits that are especially suitable for programmable logic integrated circuit devices.
2. Description of the Related Art
FIG. 1 shows a block diagram of a digital system within which the present invention may be embodied. The system may be provided on a single board, on multiple boards, or even within multiple enclosures. FIG. 1 illustrates a system (101) in which a programmable logic device (121) may be utilized. Programmable logic devices (sometimes referred to as a PALs, PLAs, FPLAs, PLDs, EPLDs, EEPLDs, LCAs, or FPGAs), are well-known integrated circuits that provide the advantages of fixed integrated circuits with the flexibility of custom integrated circuits. Such devices allow a user to electrically program standard, off-the-shelf logic elements to meet a user's specific needs. See, for example, U.S. Pat. No. 4,617,479, incorporated herein by reference. Such devices are currently represented by, for example, Altera's MAX.RTM. series of PLDs and FLEX.RTM. series of PLDs. The former are described in, for example, U.S. Pat. Nos. 5,241,224 and 4,871,930, and the Altera Data Book, June 1996, all incorporated herein by reference. The latter are described in, for example, U.S. Pat. Nos. 5,258,668, 5,260,610, 5,260,611, and 5,436,575, and the Altera Data Book, June 1996, all incorporated herein by reference. Logic devices and their operation are well known to those of skill in the art.
In the particular embodiment of FIG. 1, a processing unit (101) is coupled to a memory (105) and an I/O (111) and incorporates a programmable logic device (PLD) (121). PLD (121) may be specifically coupled to memory (105) through connection (131) and to I/O (111) through connection (135). The system may be a programmed digital computer system, digital signal processing system, specialized digital switching network, or other processing system. Moreover, such systems may be designed for a variety of applications such as, merely by way of example, telecommunications systems, automotive systems, control systems, consumer electronics, personal computers, and others.
Processing unit (101) may direct data to an appropriate system component for processing or storage, execute a program stored in memory (105) or input using I/O (111), or perform other similar functions. Processing unit (101) may be a central processing unit (CPU), microprocessor, floating point coprocessor, graphics coprocessor, hardware controller, microcontroller, digital signal processor (DSP) or programmable logic device programmed for use as a controller, or other processing unit. Furthermore, in many embodiments, there is often no need for a CPU. For example, instead of a CPU, one or more PLDs (121) may control the logical operations of the system. In some embodiments, processing unit (101) may be a computer system. Memory (105) may be a random access memory (RAM), read only memory (ROM), fixed or flexible disk media, PC Card flash disk memory, tape, or any other storage retrieval means, or any combination of these storage retrieval means. PLD (121) may serve many different purposes within the system in FIG. 1. PLD (121) may be a logical building block of processing unit (101), supporting its internal and external operations. PLD (121) is programmed to implement the logical functions necessary to carry out its particular role in system operation.
One example of a known PLD (500) is shown in FIG. 2. Device (500) may be generally like the PLD shown and described in U.S. Pat. No. 5,689,195, issued to Cliff et al., which is hereby incorporated by reference herein. Device (500) includes a plurality of regions (510) of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Each region includes a plurality of subregions (512) of programmable logic. For example, each subregion (512) may include a four-input look-up table. The table is programmable to produce a "combinatorial" output signal, which can be any logical combination of four input signals applied to the look-up table. Each subregion (512) may additionally include a register (e.g., a flip-flop) for selectively registering (storing) the combinatorial output signal to produce a registered output signal. And each subregion (512) may include programmable logic connectors ("PLCs") for programmably selecting either the combinatorial or registered output signal as the final output signal of the subregion.
A plurality of horizontal interconnection conductors (520) is associated with each row of regions (510) for conveying signals to, from, and/or between the regions in the associated row. A plurality of vertical interconnection conductors (530) is associated with each column of regions (510) for conveying signals to, from, and/or between the various rows. A plurality of local conductors (540) is associated with each region (510) for making selected signals on the adjacent horizontal conductors (520) available to the associated region.
PLCs (522) are provided for making programmable connections between selected intersecting conductors (520) and (540). A plurality of subregion feeding conductors (550) is associated with each subregion (512) for applying selected signals on the adjacent conductors (540) (and adjacent local feedback conductors (560) (described below)) to the associated subregion. PLCs (542) are provided for making programmable connections between intersecting conductors (540), (560) and (550). The output signal of each subregion (512) can be applied to selected adjacent vertical conductors via PLCs (562) and/or to selected horizontal conductors (520) via PLCs (564). The output signal of each subregion (512) is also made available as a local feedback signal (via a conductor (560)) to all of the subregions in the region (510) that includes that subregion. Selected intersecting horizontal and vertical conductors are programmably interconnectable by PLCs (532).
Another example of a known PLD (600) is shown in FIG. 3. Device (600) may be generally like the PLDs shown in U.S. Pat. No. Re. 34,363, issued to Freeman, which is also hereby incorporated by reference herein. Device (600) includes a plurality of configurable logic blocks ("CLBs") (610) disposed on the device in a two-dimensional array of intersecting rows and columns of CLBs. Each CLB (610) may include one or two small, programmable, look-up tables and other circuitry such as a register and PLCs for routing signals within the CLB. A plurality of horizontal interconnection conductor tracks (620) are disposed above and below each row of CLBs (610). A plurality of vertical interconnection conductor tracks (630) are disposed to the left and right of each column of CLBs (610). Local conductors (640) are provided for bringing signals into each CLB (610) from selected conductor tracks (620),(630) adjacent to each side of the CLB and/or for applying signals from the CLB to selected adjacent conductor tracks (620),(630). PLCs (622),(632) are provided for making programmable connections between selected intersecting conductors (620),(630) and (640). PLCs (624) are provided for making programmable connections between selected conductors segments in tracks (620) and/or (630) that intersect or otherwise come together at the locations of those PLCs. Programming of the programmable elements in devices of this type employs shift registers, where each shift register controls an associated logic or switching element. Programming data is shifted through the shift register or registers until the data desired for controlling each logic or switching element is stored in the shift register stage associated with that element. A disadvantage of this approach is that shift registers are relatively complex and require substantial numbers of conductors for interstage data transfer, clocking, etc.
In programmable logic devices such as that shown in FIG. 2, first-in/first-out ("FIFO") chains of static random access memory ("SRAM") cells are commonly used on the device for programmable control of the configuration of the device. For example, the SRAM cells in such FIFO chains may be used to control the logic performed by each subregion (512) (e.g., by constituting or controlling the data stored in the look-up tables in those components and controlling the connections made by the PLCs in those components). The SRAM cells in the FIFO chains may also be used to control the connections made by the various interconnection conductor PLCs (e.g., PLCs 522, 532, 542, 562, and 564) on the device. FIFO chains have an advantage over shift register programming as the FIFO chains have a simpler programming structure. A typical technique for programming the programmable elements in devices using FIFO chains is shown, for example, in U.S. Pat. No. 5,237,219, issued to Cliff, which is hereby incorporated by reference herein. A typical prior art FIFO SRAM chain (710) will now be described with reference to FIG. 4.
In the FIFO SRAM chain (710) shown in FIG. 4, each SRAM cell (720) includes a relatively strong, forwardly directed driver inverter (722) connected in a closed loop series with a relatively weak, backwardly directed feedback inverter (724). In the absence of a signal passed from above by an NMOS pass gate (714), each feedback inverter (724) is strong enough to hold the associated driver inverter (722) in whatever state it was left by the most recent signal passed by the pass gate (714) immediately above. On the other hand, each feedback inverter (724) is not strong enough to prevent the associated driver inverter (722) from responding to any signal passed by the pass gate (714) immediately above.
Programming data is applied to FIFO chain (710) via DATA IN line (712) at the start of the chain. Initially all of pass gates (714) are enabled by address signals ADDR-1 through ADDR-N. This allows the first programming data bit to pass all the way down the chain (inverted by each successive driver inverter (722) that it passes through) until it reaches and is stored in cell (720-N).
Pass gate (714-N) is then turned off by changing the ADDR-N signal to logic 0. The next programming data bit from line (712) therefore passes down the chain until it reaches and is stored in the cell (720-(N-1)) immediately above cell (720-N) (not shown but similar to all other cells (720)). The NMOS pass gate (714) above the cell (720-(N-1)) is then turned off and the next programming data bit is applied to the DATA IN line (712). This process continues until all of cells (720) have been programmed and all of pass gates (714) have been turned off. Each cell (720) outputs the data it stores via its DATA OUT line. These DATA OUT signals may be used to control various aspects of the operation of a programmable logic device that includes chain (710). For example, a DATA OUT signal from chain (710) may control a programmable aspect of the "architecture" of the programmable logic device (e.g., which of several available clock or clear signals a register in a subregion (512) (FIG. 2). Or a DATA OUT signal from chain (710) may control a programmable aspect of the logic performed by the device (e.g., by being a datum in a look-up table in a subregion (512) or a CLB (610)). As still another example, a DATA OUT signal from chain (710) may control an interconnection conductor PLC (e.g., a PLC 522, 532, etc. (FIG. 1)) on the device.
The contents of chain (710) may be verified by using the ADDR signals to enable pass gates (714) progressively from the bottom up. This allows the data in cells (720) to be read out one after another from the bottom up via VERIFY lead (716).
It will be apparent from the foregoing that in order to program or verify chain (710) each NMOS pass gate (714) must be able to effectively pass both logic 0 and logic 1 signals. When circuit components are made very small (as is becoming possible as a result of ongoing advances in the techniques for semiconductor fabrication) and VCC (the power voltage used for logic 1 signals) is accordingly reduced, an NMOS pass gate (714) may not be able to pass a logic 1 signal that is sufficiently strong to overwrite the logic 0 output of the feedback inverter (724) below it unless the pass gate is made undesirably large. Thus PMOS pass gate does not pass logic 0 very well under the above-described conditions that reduce the effectiveness of an NMOS pass gate in passing logic 1. FIFO SRAM chains are therefore becoming less satisfactory for use as the programmable elements in products such as programmable logic devices.
Accordingly, it is desired that the present invention overcome the limitations of current FIFO cells and related programmable logic devices.